This paper proposes an efficient scheme of slot timing in slotted rings based on the register insertion method. The scheme minimizes the time necessary for relaying packets at intermediate nodes and therefore decreases the packet delay.
A performance model of the slotted ring is presented, which is analyzed by means of the equilibrium point analysis (EPA) method. Good agreement between analytic and simulation results is observed. It is also shown that the proposed timing scheme outperforms a scheme previously studied.